1. Field of the Invention
The present invention relates to data processing systems, and more specifically to scheduling tasks for execution by a processor of a data processing system.
2. Background Information
A data processing system typically comprises one or more processing elements (i.e., processors) and a memory for storing software programs and data structures. An operating system (OS), typically resident in the memory and executed by each processor, functionally organizes the data processing system by, inter alia, invoking operations in support of software processes, tasks, and/or routines (hereinafter “tasks”) executed by the processor. A known way to switch between tasks executed by the processor involves the use of an asynchronous signal, or “interrupt”. A conventional interrupt controller generates the interrupt, typically in response to an external event. The OS typically processes the interrupt and dispatches an interrupt service routine to the processor. Thereafter, the processor typically invokes a context switch prior to executing the service routine. As used herein, a context switch (or “context switching”) generally denotes (i) suspending execution of a task currently running on the processor, (ii) saving a state of the suspended task, (iii) retrieving a state of a new task (“service routine”), and (iv) executing the new task.
The amount of time required to switch processor tasks is typically referred to as the “interrupt latency”. Factors that influence interrupt latency include arbitration among various interrupt controllers seeking (interrupt) access to the processor, as well as overhead associated with context switching. Lower interrupt latencies correspond to less time required to switch among tasks (i.e., faster task switching).
As the need for reliable high-speed processing of multiple tasks increases, a conventional OS may have an unpredictable and/or undesirably high interrupt latency. This unpredictable and/or high interrupt latency may limit the effectiveness of the data processing system, particularly in the case of an embedded data processing system. As used herein, an embedded data processing system includes a processor that is implemented within a device controlled by the processor. For example, an embedded data processing system may be implemented as a Fibre Channel (FC) host bus adapter (HBA). In such an implementation, high interrupt latencies may reduce the possible throughput/bandwidth of the HBA, especially if, e.g., different tasks are associated with sending and/or receiving signals from different ports of the HBA.
To reduce the interrupt latency during task switching, an embedded data processing system may utilize a Real-Time Operating System (RTOS) in place of the conventional OS. An RTOS typically employs specialized scheduling algorithms to decrease interrupt latency, and, when implemented with appropriately programmed software, may substantially stabilize and increase the predictability of task switching. However, a noted drawback of both a conventional OS and an RTOS is that they both consume memory which, in turn, adds cost and complexity, as well as consumes power. Moreover, because these prior art methods require use of an operating system to process the interrupt and schedule the task switch, the interrupt latency may still be undesirably high.